Bibtex de la publication

@InProceedings{ BaLaRoSa2006.3,
author = {Barre, Jonathan and Landet, Cédric and Rochange, Christine and Sainrat, Pascal},
title = "{Modeling Instruction-Level Parallelism for WCET Evaluation}",
booktitle = "{IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), Sidney, 16/08/06-18/08/06}",
year = {2006},
month = {août},
publisher = {IEEE},
address = {http://www.ieee.org/},
pages = {61--67},
language = {anglais},
URL = {http://www.irit.fr/publis/TRACES/6668_rtcsa06.pdf},
note = {TA=32(regular)/101 = 30% (+21 short)},
abstract = {The estimation of the Worst-Case Execution Time of hard real-time applications becomes very hard as more and more complex processors are used in real-time systems. In modern architectures, estimating the execution time of a single basic block is not trivial due to possible timing anomalies linked to out-of-order execution. The influence of preceding basic blocks on the pipeline state also has to be accounted for. Recently, graphs have been used to model the execution of a block on a dynamically-scheduled pipelined processor [11]. In this paper we extend this model to express instruction-level parallelism so that superscalar processors with multiple functional units can be analyzed. Simulation results show how this extended model estimates WCETs tightly even when a realistic processor is considered. They also give an insight into the complexity of the model in terms of analysis time.}
}